The present invention generally relates to semiconductor devices, and, more particularly, to a semiconductor device that includes a plurality of function blocks, and address and data buses connected to the function blocks.
As electronic devices are expected to have a larger variety of functions, there is an increasing demand for semiconductor devices having more functions and greater expandability. In an attempt to realize this, a large number of function blocks are connected to a single bus in a semiconductor device of the prior art, and each control operation for each corresponding function block is performed through the single bus.
FIG. 1 shows the structure of a conventional semiconductor device. As shown in FIG. 1, the conventional semiconductor device includes a bus control unit 10, an address/data bus 11, and a plurality of function blocks 12. The bus control unit 10 serves as a control unit such as a CPU that controls the function blocks 12 via the address/data bus 11. In the address space that is controlled by the bus control unit 10, each function block 12 is allocated to each corresponding address area. When the bus control unit 10 accesses an address area, the corresponding function block 12 performs a predetermined control operation. Each function block 12 is provided with a latch/decoder unit 12a that latches and decodes an address transmitted via the address/data bus 11, and determines whether the access is intended for the corresponding function block 12.
As described above, the conventional semiconductor device has the function blocks 12 connected directly to the address/data bus 11, so that the latch/decoder unit 12A of each function block 12 can determine whether each access is intended for each corresponding function block 12.
In this structure, as the number of function blocks 12 increases, the load on the address/data bus 11 also increases. Since there is only one address/data bus in this structure, a large number of function blocks 12 will cause a problem of a large load on the address/data bus 11. To avoid such a problem, the semiconductor device needs to be equipped with a bus driver that exhibits sufficiently high driving performance for a large number of function blocks 12.
Furthermore, to connect a large number of function blocks 12 to the single address/data bus 11, a large number of latch/decoder units 12a having identical structures are required, and this results in an increase in circuit size. Also, the greater wire length causes wiring delay, which hinders high-speed operations and results in larger electric power consumption and frequent noise.
Also, since the function blocks 12 are connected to the single address/data bus 11, one access operation is effective only for one of the function blocks 12. For instance, a transferring operation between two of the function blocks 12 requires two cycles by the bus control unit 10, with one of the two cycles being a read cycle for one of the two function blocks 12, and the other one of the two cycles being a write cycle for the other one of the two function blocks 12. During these two cycles, the address/data bus 11 is continuously occupied. While the address/data bus 11 is thus occupied, no accesses can be made to another function block 12, and no data can be transferred between another two function blocks 12. Apparently, the fact that one transferring operation requires two cycles hinders improvement of the semiconductor device.